<?xml version="1.0" encoding="UTF-8"?><rss version="2.0"
	xmlns:content="http://purl.org/rss/1.0/modules/content/"
	xmlns:dc="http://purl.org/dc/elements/1.1/"
	xmlns:atom="http://www.w3.org/2005/Atom"
	xmlns:sy="http://purl.org/rss/1.0/modules/syndication/"
	
	>
<channel>
	<title>
	「FPGA——逻辑分析仪（纯verilog实现）」的评论	</title>
	<atom:link href="/fpga-%E9%80%BB%E8%BE%91%E5%88%86%E6%9E%90%E4%BB%AA%EF%BC%88%E7%BA%AFverilog%E5%AE%9E%E7%8E%B0%EF%BC%89/feed/" rel="self" type="application/rss+xml" />
	<link>/fpga-%e9%80%bb%e8%be%91%e5%88%86%e6%9e%90%e4%bb%aa%ef%bc%88%e7%ba%afverilog%e5%ae%9e%e7%8e%b0%ef%bc%89/</link>
	<description></description>
	<lastBuildDate>Tue, 30 Dec 2025 19:02:45 +0000</lastBuildDate>
	<sy:updatePeriod>
	hourly	</sy:updatePeriod>
	<sy:updateFrequency>
	1	</sy:updateFrequency>
	<generator>https://wordpress.org/?v=6.9.4</generator>
</channel>
</rss>
